Joel Darnauer Resume January 2007

Joel Darnauer
joeld@stanford.edu
Cell 650 714 7688
January 2010

I'm interested in game-changing projects
where I can meet smart, energetic people and have a
positive impact on the world.

I'm currently working on a new way of visualizing web traffic.
My long-term vision is to see what users are doing on a planetary scale.

PLACES I'VE BEEN

Google. Hardware/Software Engineer. Grunt. June 2008-Present.

Current project is user interface logs analysis and internal site analytics.
[MySql, Python, C++, SVG, JS, log analysis, web analytics]
Prior projects were in server and networking design for datacenters. Hardware and board design, linux firmware and kernel hacking.
[10GigE, PCI Gen2, BERT, VNA, TDR/TDT, Sampling scopes]

Kiss Me LLC. Founder. Jan 2008-June 2008.

I started a small LLC with two partners after our app from the Stanford Facebook class reached 1M installed users.
Responsible for day to day operation of the business including all development, site reliability, partner relationships and monetization.
Sold my stake in the business :)
[Linux, Ajax, Mysql, Php, FBML, Moxie]

Stanford University, Electrical Engineering. March 2005-Present.

I continue taking classes at Stanford to stay fresh and keep an eye out.
So far I have studied human computer interfaces, medical imaging (MRI), computer vision, machine learning, facebook, and neuroscience.
My most recent class is developing iPhone Apps for mobile music. (Xcode, Iphone, Objective C)
Also experienced in Matlab signal processing and image processing toolboxes, Visual C++, and some C#.

Juniper Networks, Sunnyvale, CA. June, 1999-March, 2005.
Senior Board Design/Signal Integrity Engineer.

Designed several networking cards for the for the T-series and M-series family of high-performance routers. [Viewlogic, Allegro, FPGA design (Xilinx/Altera), Network and spectrum analyzers, TDR/TDT, BERTs, and high speed scopes. ]
Responsible for design, vendor management, schematics lab bringup, diagnostics and qualification, manufacturing test support.
Working knowledge of PCB layout and design, circuit simulation (hspice), general CMOS circuits, high-speed IO timing, transmission lines, high speed clocking, crosstalk, PLLs, jitter and PCB noise.

Also:

Silicon Graphics. Engineer - signal integrity and computer aided design. 1996-1999.
Micromodule Systems. Engineer - computer-aided design. 1995-1996.
AT&T Bell Laboratories. Multi-chip module design. Summer 1994.
University of California at Santa Cruz. MS, PhD - Computer Engineering. 1991-1997.
University of California Santa Barbara. BS - Electrical and Computer Engineering. 1986-1991.

PUBLICATIONS

Journal Articles

"A Silicon-On-Silicon Field Programmable Multichip Module (FPMCM)---Integrating FPGA and MCM Technologies". Joel Darnauer, Porfirio Garay, Tsuyoshi Isshiki, John Ramirez, Wayne Wei-Ming Dai. IEEE Transactions on Components, Packaging, and Manufacturing Technology Part B. November 1995, Volume 18, Issue 4.
"Electrical evaluation of flip-chip package alternatives for next-generation microprocessors". Joel Darnauer, Dave Chengson, Bill Schmidt, Ed Priest, Dave Hanson, and Bill Petefish. IEEE Transactions on Advanced Packaging, August 1999.

Conference Papers

"Electrical evaluation of flip-chip package alternatives for next-generation microprocessors". Joel Darnauer, Dave Chengson, Bill Schmidt, Ed Priest, Dave Hanson, and Bill Petefish. 1998 Electronic Components and Packaging Technology Conference.
"Tradeoffs in Chip and Substrate Complexity and Cost for Field Programmable Multichip Modules -Part II: The Clique Architecture". Joel Darnauer and Wayne Wei-ming Dai. ASME Interpack. June, 1997.
"Tradeoffs in Chip and Substrate Complexity and Cost for Field Programmable Multichip Modules". Joel Darnauer and WayneWei-ming Dai. First Workshop on Innovative Systems In Silicon. October, 1996
"A Method for Generating Random Circuits and its Application to Routability Measurement". Joel Darnauer and Wayne Wei-ming Dai. 1996 ACM Symposium on Field Programmable Gate Arrays.
"Field Programmable Multi-chip Module: an Integration of FPGA and MCM technology". Joel Darnauer, Porfirio Garay, Tsuyoshi Isshiki, John Ramirez, Wayne Wei-Ming Dai. 1995 Multi-Chip Module Conference.
"Design of FPGAs with Area I/O for Field Programmable Multi-chip Module". Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai. 1995 Symposium on Field Programmable Gate Arrays.
"A First-Generation Field Programmable Multichip Module". Joel Darnauer, Porfirio Garay, Tsuyoshi Isshiki, John Ramirez, Wayne Wei-Ming Dai. 1994 IEEE Workshop on FPGAs for Custom Computing Machines.
"Fast Pad Redistribution from Periphery-IO to Area-IO". Joel Darnauer and Wayne Wei-Ming Dai. 1994 IEEE Multi-Chip Module Conference.
"A 1024-Pin Plastic Ball Grid Array for Flip Chip Die". Andy Switky, Vijay Sajja, Joel Darnauer, Wayne Wei-Ming Dai. 1994 Electronic Components and Technology Conference.

Dissertation

Cost-Effective Architectures for Field-programmable Multi-chip Modules." Joel Darnauer. University of California at Santa Cruz, Computer Engineering Board of Studies, March 1997.

Technical Reports

"Planar Interchangeable 2-Terminal Routing". UCSC CRL Technical Report 95-49. October, 1995. Man-Fai Yu, Joel Darnauer, and Wayne Wei-Ming Dai.
"The Planar Pin-Assignment and Routing Problem is NP-complete". UCSC CRL Technical Report 95-41. August, 1995. Joel Darnauer.